
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// -----------------------------------------------------------------------------
// Project Name : 
// Author 		: HiDark
// File   		: forward.sv
// Create 		: 2023-04-21 10:53:10
// Revise 		: 2023-04-21 10:53:10
// Abstract 	: 
// -----------------------------------------------------------------------------
`include "defines.svh"
module forward(
	input	logic	[ 4:0]	rs1_if2id,
	input	logic	[ 4:0]	rs2_if2id,

	input	logic	[ 4:0]	rs1_id2ex,
	input	logic	[ 4:0]	rs2_id2ex,
	input	logic	[ 4:0]	wb_addr_ex2mem,
	input	logic			wb_en_ex2mem,
	input	logic	[ 4:0]	wb_addr_mem2wb,
	input	logic			wb_en_mem2wb,

	output	logic	[ 1:0]	forwardA,
	output	logic	[ 1:0]	forwardB
);


//=================================================================================
// Signal declaration
//=================================================================================


//=================================================================================
// Body
//=================================================================================
	
// Operation data hazard

	always_comb	begin
		if (wb_addr_ex2mem == rs1_id2ex&&wb_en_ex2mem&&wb_addr_ex2mem!=5'd0)
			forwardA	=	`FORWARD_ONE;
		else if (wb_addr_mem2wb == rs1_id2ex
				&&wb_en_mem2wb&&wb_addr_mem2wb!=5'd0
				&&(wb_addr_ex2mem != rs1_id2ex||!wb_en_ex2mem))
			forwardA	=	`FORWARD_TWO;
		else
			forwardA	=	`FORWARD_ZERO;			
	end

	always_comb	begin
		if (wb_addr_ex2mem == rs2_id2ex&&wb_en_ex2mem&&wb_addr_ex2mem!=5'd0)
			forwardB	=	`FORWARD_ONE;
		else if (wb_addr_mem2wb == rs2_id2ex
				&&wb_en_mem2wb&&wb_addr_mem2wb!=5'd0
				&&(wb_addr_ex2mem != rs2_id2ex||!wb_en_ex2mem))
			forwardB	=	`FORWARD_TWO;
		else
			forwardB	=	`FORWARD_ZERO;			
	end




endmodule